Embodiments of the present inventive subject matter relate in general to the field of digital memory circuits, and in particular to reduced power consumption in memory.
Static random access memory (SRAM) is a type of volatile digital memory that retains data written to it so long as power is applied to the SRAM. One type of SRAM commonly used in high performance computational circuits is referred to as a “domino” SRAM.
Cells in a domino SRAM design are arranged into groups of cells, typically on the order of eight to sixteen cells per group. Each cell in a group is connected to a local bit line pair. The local bit line pair for each group of cells is coupled to a global bit line pair. Rather than use a sense amplifier to detect a differential voltage when reading a cell, the local bit lines in a domino SRAM are precharged and discharged by the cell in a read operation. The discharge is detected and determines the state of cell. The local bit line, the precharge circuitry, and the detection circuitry define a dynamic node of the domino SRAM.
FIG. 5 depicts a ripple domino read scheme of an SRAM cell 12.1. Referring to FIG. 5, a read operation starts with a rising word line at the SRAM cell 12.1. The SRAM cell 12.1 pulls down the local bit line (lbl) 16. The local bit line 16 is connected to a local evaluation circuit 14, which acts as an amplifier for the read signal. The local evaluation circuit 14 comprises an amplifier and gate controlled by a read enable signal rdt. Also the local evaluation circuit 14 comprises a pull-down-NFET 14.2 controlled by a signal dt to pull down a global bit line gbl′ which is a high capacity node due to the long wiring length and the device capacitance of the local evaluation circuit pull-down devices. The global bit line gbl′ is the biggest contributor for active and passive power consumption in ripple domino SRAM arrays.
The SRAM cells 12.1 on the word line are read out all at the same time in spite of the fact that only the information of one set is needed at the output. For a data cache using a given number of N global bit lines gbl′, only one of the N possibly discharged global bit lines gbl′ is read out. A N:1-way multiplexer 22 is used to choose the global bit line gbl′ to read based on a control signal. Further, a global bit line restore and latch device 40′ is used to charge the global bit line gbl′ which comprises a pull-up-PFET 42′, a latch 44′ and an inverter 46′. Additionally a redundancy multiplexer 30′ is used to decide which global bit line is fed as input signal into the N:1-way multiplexer 22 based on a defect signal indicating whether the global bit line gbl′ is found to be defective or not defective. The global bit line gbl′ is the output signal muxed_gbl′ of the redundancy multiplexer 30′ if the global bit line gbl′ is found to not be defective, and a redundant global bit line gbl+2′ is used as the output signal muxed_gbl′ of the redundancy multiplexer 30′ if the global bit line gbl′ is found to be defective. The global bit lines, which are the main contributor to power consumption, are charged every cycles to the level of the power supply voltage.